EMEA 2021 https://www.tinyml.org/event/emea-2021
Bottom-up and top-down neural processing systems design: unveiling the road toward neuromorphic intelligence
Charlotte FRENKEL, Postdoctoral Researcher, Institute of Neuroinformatics
While Moore’s law has driven exponential computing power expectations, its nearing end calls for new roads to embedded cognition. The field of neuromorphic computing aims at a paradigm shift compared to conventional von-Neumann computers, both for the architecture (i.e. in-memory computing) and for the data representation (i.e. spike-based event-driven encoding). In this talk we will show how to best exploit a bottom-up (neuroscience-driven) approach and a top-down (application-driven) one toward embedded cognition and neuromorphic intelligence. The talk is thus divided in two parts.
In the first part we will focus on the bottom-up approach. From the building-block level to the silicon integration, we design two digital time-multiplexed spiking neural network processing devices: ODIN and MorphIC. Furthermore, we explore the design of neuromorphic processors that use mixed-signal analog-digital circuits and temporal dynamics matched to the one of their input signals, without having to resort to time-multiplexing. We demonstrate with silicon measurement results that hardware-aware neuroscience model design and selection allows optimizing a tradeoff between biophysical versatility, neuron and synapse densities, and power consumption.
In the second part of this talk we will follow a top-down approach. By starting from the applicative problem of adaptive edge computing, we derive a learning algorithm optimized for low-cost on-chip learning: the Direct Random Target Projection (DRTP) algorithm. With silicon measurement results of a top-down DRTP-enabled neuromorphic processor codenamed SPOON, we demonstrate that combining event-driven and frame-based processing with weight-transport-free update-unlocked training supports low-cost adaptive edge computing with spike-based sensors.
Therefore, each of these two design approaches can act as a guide to address the shortcomings of the other. We compare them and discuss their tradeoffs for different potential use cases in edge computing.